1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the invention relates to a minute nonvolatile semiconductor memory device, fabrication method for the same, semiconductor integrated circuits and systems which include a memory cell unit (NAND cell) that is configured with a plurality of memory cells connected to each other, and select transistors doped with impurities in their respective channel regions.
2. Description of the Related Art
Conventionally, for example, an electrically erasable programmable read-only memory (EEPROM), which electrically writes and erases data, is known as a nonvolatile semiconductor memory device. In the EEPROM, in particular when it is a NAND type, a memory cell array is configured by arranging memory cells at the respective points of intersecting column lines and row lines. A MOS transistor having a stacked gate structure configured by stacking layers of a floating gate and a control gate is used as a memory cell.
The EEPROM includes an electrically erasable flash memory. Much of the flash memory in use is NAND flash memory with highly increased integration.
A representative memory cell of a NAND flash memory is described, for example, in R. Shirota, “A Review of 256 M-bit NAND Flash Memories and NAND Flash Future Trend”, Non-Volatile Semiconductor Memory Workshop (NVSMW) 2000, pp 22-31.
The nonvolatile semiconductor memory device has a circuit configuration such as that shown in the circuit diagram of FIG. 1. As shown in FIG. 1, in the memory cell unit of the NAND flash memory, a plurality of, for example, sixteen memory cell transistors M0 to M15 form a memory block 70, which is indicated by the region enclosed by the dotted line. The memory cells are connected in series with a bit line side select transistor SG1 connected to one side and a source line side select transistor SG2 connected to the other.
Each word line WL0 to WL15 makes a one-to-one connection to the gates of memory cell transistors M0 to M15, respectively. A select gate line SGD is connected to the gate of the bit line side select transistor SG1. A select gate line SGS is connected to the gate of the source line side select transistor SG2.
The source of the bit line side select transistor SG1 is connected to a bit line DQ which functions as a data line. The source of the source line side select transistor SG2 is connected to a common source line CS.
While not shown in the figures, a plurality of NAND strings 70 are connected in the direction in which the bit line DQ extends. In addition, a plurality of NAND strings 70 with the same circuit configuration are formed for every bit line DQ in the direction in which word line WL0, WL1, WL2, . . . , WL15 extend.
A plurality of NAND strings 70 are vertically connected in series with contacts provided at the respective ends of the NAND strings to give a plurality of consecutive configurations where memory cell transistors are connected via the bit line side select transistor SG1 and the source line side select transistor SG2, on both ends.
A plurality of word lines WL0, WL1, WL2, . . . , WL15 for memory cell gates are arranged in lines parallel to each other. At each end of the plurality of memory cell gates, respective select gate lines SGD and SGS are formed in lines parallel to each other, and parallel to the word lines WL0, WL1, WL2, . . . , WL15 for memory cell gates. In this case, the memory cell transistors M0, M1, M2, . . . , M15 have equal gate lengths, respectively. In addition, each of the pairs of the select gate transistors SG1, SG2 on both sides of the memory cell transistors M0, M1, M2, . . . , M15 have the same gate length, and the gate length of the select gate transistors SG1, SG2 is generally formed so as to be longer than the gate length of the memory cell transistor.
Spaces F (F being the minimum fabrication dimension) having the same width are formed between a plurality of word lines WL0, WL1, WL2, . . . , WL15 for memory cell gates. This space F is equal to the gate length of the memory cell gate. Moreover, the spaces F, which equal the spaces F between the memory cell gates, are formed between the select gate and memory cell gate adjacent to the select gate.
Device activation regions are formed parallel to each other and perpendicular to the direction in which the memory cell transistors M0, M1, M2, . . . , M15 extend. Such device activation regions are segmented into multiple regions by a plurality of device isolation regions formed parallel to each other and perpendicular to the memory cell gate.
In this case, one NAND string is configured by forming a pair of individual select gates at each end of a plurality of, for example, sixteen memory cell gates. Another NAND string is formed on the end of this NAND string providing a space of approximately 2F, which is approximately twice the space F formed between the memory cell gates. In this case, contacts are formed above the device activation regions between neighboring select gates of the NAND strings.
In this manner, all gate lengths are formed with uniform lines and spaces, and arranged with the same pitch within the memory cell unit. In addition, the channel length of the select gate is miniaturized so as to be the same size as that of the memory cell gate. The select gate is configured from two adjacent gates and functions as a select transistor. In this case, in the conventional nonvolatile semiconductor memory device, since the select gate length itself is approximately 2F and is on both the source side and drain side, which provides a space of approximately 4F, then adding the space separating the neighboring select gates of another memory cell gate of approximately 2F to this gives a total space of approximately 6F. Generally, the select gate is longer than the gate length of the memory cell transistor, effectively preventing degradation in the cut-off characteristics of a transistor due to a short-channel effect.
As shown in FIG. 1, a plurality of memory cell transistors connected in series can provide a NAND cell (a memory cell unit). The source and drain regions of each memory cell are connected in series through diffused regions fabricated in the memory device substrate region.
However, there are problems with the above conventional nonvolatile semiconductor memory device. The configuration described above results in the NAND strings having irregular lines/spaces in their select gate sections, which causes fabrication margins to decrease when patterning the select gates with lithography, as micro- and/or nano-fabrication continues to progress. When designed with irregular patterns, there may be limits placed on miniaturization. In other words, if the minimum line width based on the limits of microscopic processing technology is given as F, the gate lengths of memory cell transistors, gate intervals of memory cell transistors, and spaces between the gates of the memory cell transistors and the gates of the select transistors are all formed so as to have the width F. However, the gate width of the select transistors is formed so as to b wider than F, such as 2F, to improve cut-off characteristics. This results in the presence of irregular line widths and space widths. In other words, in the case where the lines/spaces of the memory cell gates are 1F and the gate length of the lines/spaces of the select gates is approximately 2F, the gate length for the memory cell gates adjacent to the select gates is over-etched during lithography in the manufacturing process. Accordingly, the memory cell gates cannot be formed to the desired length, and the required characteristics cannot be obtained. Therefore, there is no other option except to design all gate lengths with a value larger than the minimum line width F, which results in an increased surface area for the memory cell transistor region.
Moreover, there are times when the result is a NAND flash memory cell unit structure where the control gates (word lines) adjacent to the select transistors are fabricated longer or shorter than the desired value. This is because the regular pattern of word line gate lengths and spaces, being broken near the select transistor, makes uniform processing impossible. That is, if the control gates (word lines) near the select transistor are longer or shorter than the desired value, the characteristics of that memory cell differ from the characteristics of other memory cells, which affects write/erase/read operations and invites problems in terms of reliability.
In addition, if the regular patterns are broken, problems, such as a breakdown of the resist during the developing process of the resist after photolithography processing, can give rise to an electrical shorting problem between the adjacent gate electrodes.